A portion of the disclosure of this patent document contains command formats and other computer language listings all of which are subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.
The invention relates to electronic circuits More particularly, the invention relates to simulation and determination of design parameters of an electronic circuit.
A latch is a circuit element that maintains a particular state between state changing events, i.e., in response to a particular input, and is ubiquitous in digital sequential circuit designs. For example, as shown in FIG. 1, a typical latch 100 may include, inter alia, a forward inverter 101, a feedback inverter 102, an input terminal 103 and an output terminal 104. The output voltage level, VOUT, remains at a particular voltage level, i.e., either high or low, until an input signal, VIN, is received at the input terminal 103, at which time the state of the output may change depending on the nature of the input signal. For example, the state of the output 104 may change from a high state to a low state upon receipt of a logical high signal at the input 103.
In order for the latch to operate properly, i.e., to change state upon receiving a particular input, the input signal levels to the latch must exceed certain thresholds with a sufficient margin. To this end, during a circuit design, it must be ensured that the input signal levels delivered through various signal paths to each of latches in the circuit under design meet the above input signal margin.
One of the ways to ensure satisfaction of the above input signal level requirement is to determine what is often referred to as the xe2x80x9cDC marginxe2x80x9d for each of the latches present in the circuit being designed. The DC margin is a pair of values, the one margin and the zero margin. The one margin is the difference between the trip voltage (Vtrip) of the forward inverter 101 of the latch 100 and the worst case pull-up input signal level that may be presented to the latch. The zero margin is the difference between the Vtrip of the forward inverter 101 and the worst case pull-down input signal level that may be presented to the latch 100. The trip voltage Vtrip is defined as the equilibrium voltage level of the output voltage level and the input voltage level of the forward inverter. In order for a particular circuit design to be deemed acceptable, the DC margin must exceed a minimum margin according to a design guideline.
Unfortunately, heretofore, in order to determine the DC margin of a latch, every possible signal paths from each of the possible circuit elements that may drive the latch must be examined, requiring performance of simulations, using a simulation program, e.g., the SPICE(trademark), for each of the possible signal paths. The prior attempts to determine the DC margin requires numerous simulations, each of which takes a long time to perform, and are thus inefficient and time consuming. This problem may be exacerbated if there are numerous latches in the particular circuit under design.
Thus, there is a need for more efficient method of determining DC margin of a latch, which does not require numerous simulations for every possible signal paths to the latch.
In accordance with the principles of the present invention, a method of determining a DC margin of a latch comprises performing a first simulation using a first simulation circuit to determine a trip voltage of a forward inverter of the latch, performing a second simulation using a second simulation circuit to determine a one margin of the latch, the second simulation circuit comprising a worst case pull-up signal path, and performing a third simulation using a third simulation circuit to determine a zero margin of the latch, the third simulation circuit comprising a worst case pull-down signal path.
In accordance with another aspect of the principles of the present invention, a computer program stored on a computer readable storage medium implements a method of determining a DC margin of a latch, and comprises a set of instructions for performing a first simulation using a first simulation circuit to determine a trip voltage of a forward inverter of the latch, performing a second simulation using a second simulation circuit to determine a one margin of the latch, the second simulation circuit comprising a worst case pull-up signal path, and performing a third simulation using a third simulation circuit to determine a zero margin of the latch, the third simulation circuit comprising a worst case pull-down signal path.
In yet another aspect of the principles of the present invention, a simulation circuit for determining a DC margin of a latch comprises a latch portion representing the latch being simulated, the latch portion comprising a forward inverter and a feedback inverter, an input of the forward inverter being operably connected to an input of the latch portion, and an input of the feedback inverter being operably connected to an output of the latch portion, a driver portion representing a driver circuit element capable of supplying an input signal to the latch being simulated, and a pass path subcircuit configured to receive a drive signal from the driver portion, and configured to supply the drive signal to the input of the latch portion, the pass path subcircuit representing one or more pass circuit elements along a worst case signal path between the driver circuit element and the latch being simulated.